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W9412G6JH
12.6 Mode Register Set (MRS) Timing
CLK
CLK
t MRD
CMD
MRS
NEXT CMD
ADD
A0
Register Set data
Burst Length
A2
A1
A0
Sequential
Interleaved
A1
A2
A3
Burst Length
Addressing Mode
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
2
4
8
Reserved
2
4
8
1
0
0
A4
1
1
0
1
1
0
Reserved
Reserved
A5
A6
CAS Latency
1
1
A3
1
Addressing Mode
A7
"0"
Reserved
0
1
Sequential
Interleaved
A8
A9
"0"
DLL Reset
A6
0
A5
0
A4
0
CAS Latency
Reserved
0
0
1
A10
"0"
Reserved
0
1
0
2
0
1
1
3
A11
"0"
1
0
0
4
BA0
BA1
"0"
"0"
Mode Register Set
or
Extended Mode
Register Set
1
1
1
0
1
1
1
0
1
Reserved
2.5
Reserved
* "Reserved" should stay "0" during MRS cycle.
- 39 -
BA1
0
0
1
1
A8
0
1
BA0
0
1
0
1
DLL Reset
No
Yes
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
Reserved
Publication Release Date: Jan. 14, 2014
Revision: A04
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